--counter with 7 seven segment display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT (clk, reset : IN STD_LOGIC;
digit : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END counter;
-------------------------------------------------
ARCHITECTURE counter OF counter IS
signal count:integer range 0 to 30000000:=0;
signal clk2: std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
count<=count+1;
if(count=29999999) then
count<=0;
clk2<= not clk2;
end if;
END IF;
end process;
PROCESS(clk2, reset)
VARIABLE temp: INTEGER RANGE 0 TO 10;
BEGIN
---- counter: ---------------------
IF (reset='1') THEN
temp := 0;
ELSIF (clk2'EVENT AND clk2='1') THEN
temp := temp + 1;
IF (temp=10) THEN
temp := 0;
END IF;
END IF;
---- BCD to SSD conversion: -------
CASE temp IS
WHEN 0 => digit <= "1111110"; --7E
WHEN 1 => digit <= "0110000"; --30
WHEN 2 => digit <= "1101101"; --6D
WHEN 3 => digit <= "1111001"; --79
WHEN 4 => digit <= "0110011"; --33
WHEN 5 => digit <= "1011011"; --5B
WHEN 6 => digit <= "1011111"; --5F
WHEN 7 => digit <= "1110000"; --70
WHEN 8 => digit <= "1111111"; --7F
WHEN 9 => digit <= "1111011"; --7B ;
WHEN OTHERS => digit<="0000000" ;
END CASE;
END PROCESS;
END counter;
